Intel CEO Pat Gelsinger today spoke at the third Intel Innovation Day about what Intel will achieveayeThe ubiquitous technology of artificial intelligence has promoted the popularization of AI on various workloads such as client, terminal, network, and cloud. He emphasized that in the last five years,WaferOutput value has increased five-fold, but over the next 10 years, AI will help drive a “siliconomy” that will bring a 15-fold increase in chips and software.
Kissinger said in his keynote speech that AI represents a generational shift, and with it a new era of global expansion, with computing becoming the foundation of a better future. Developers will face huge social and business opportunities and will be able to break boundaries to solve major global challenges and improve lives for all.
In Gelsinger’s opening keynote address to developers, he mentioned that Intel will combine its hardware products with AI through open, multi-architecture software solutions. He also emphasized that AI helps drive the “silicon economy” that continues to grow through chips and software. Chips have created an industry worth US$574 billion, leading the global technology economy to an output value of nearly US$8 trillion.
Kissinger also noted that Intel previously proposed a four-year, five-node process development goal, which is currently progressing as planned. Intel 7 has entered the mass production stage, Intel 4 is now ready for mass production, and Intel 3 is also planned. Launching later this year.
Since Intel will open the Intel Foundry Services (IFS) business to accept 3 wafer foundry customers, it also highlights Intel’s determination to use advanced processes to seize the wafer foundry field.
Gelsinger also showed the Intel 20A wafer and the first test chips of the Intel Arrow Lake processor scheduled to launch next year. The Intel 20A will be the first process node to use Intel’s PowerVia chip back-side power supply technology and a new generation of RibbonFET surround gate transistor design.
As for Intel 18A, which also uses PowerVia and RibbonFET, it is planned to enter mass production in the second half of 2024. Since Intel’s 18A, it is closerTSMC2nm, although Intel announced mass production plans a year ahead of TSMC, it is generally expected that the two parties will not officially compete until the second half of 2025.
Although Intel has shown its decision to share foundry maps, Intel and TSMC are in a relationship of both competition and cooperation.
Intel also demonstrated test chip packaging manufactured by UCL Packaging Alliance. Gelsinger also predicts that the next wave of Moore’s Law will occur with multi-chip packaging. If open standards can further increase IP integration, the timeline is expected to shorten.
He said more than 120 manufacturers responded to the UCLE standard drafted last year, allowing smaller chips from different manufacturers to operate together. The new design will meet the expansion needs of various AI workloads.
He further explained that the test chip includes an Intel UCle IP chip built with the Intel 3 process and the Synopsys UCIe IP chip built with TSMC’s latest mass-produced N3E process node, and uses Intel 2.5D EMIB advanced packaging technology , which shows TSMC’s support. , Xinhe and Intel Foundry Services (IFS) built an open standardized chip ecosystem for Ucle.
In addition, Intel also demonstrated its revolutionary innovation in new packaging technology and announced the completion of glass substrates as a new generation packaging substrate. This is a major innovation that Intel considers an extension of Moore’s Law. Intel also previously announced that this breakthrough in material limitations is expected to lead to the launch of packaging technology based on glass substrate from 2026 to 2030, which will allow shrinking transistors into packages to meet data-intensive, high-performance needs. Will allow. workloads like AI, and fueling Moore’s Law expansion to 2030 and beyond.